High speed serial interfaces require a very accurate and clean clock to sample incoming data with the accuracy necessary to guarantee proper capturing of data. These high speeds make the use of an at-speed clock impractical. Many interfaces have resorted to half-rate clocks where data is sampled on both edges of the clock. This puts extremely tight requirements on the duty cycle error of the clock that reaches the samplers. Without special attention, device mismatches in a phase locked loop (PLL) and traditional clock trees can result in duty cycle error greater than acceptable limits (e.g., in excess of 10%).
FIG. 1 illustrates an example buffer 100 that may be used in a clock tree for a differential clock signal. The buffer 100 includes first, second and third transistors 110, 115, 120 and first and second resistors 130, 135. The first transistor 110 is coupled between a first voltage source (e.g., ground) 160 and the second and third transistors 115, 120. The gate of the first transistor 110 is coupled to an enable signal 165 and a reference current 170. The second and third transistors 115, 120 are coupled to the first and second resistors 130, 135 respectively; and the first and second resistors 130, 135 are coupled to a second voltage source (e.g., Vcc) 175. The gates of the second and third transistors 115, 120 receive an input signal (e.g., each transistor 115, 120 receives a different leg of the differential input signal). An output is the drain of the second and third transistors 115, 120 respectively (e.g., each transistor 115, 120 outputs a different leg of the differential output signal). The transistors 110, 115, 120 are negative channel transistors (e.g., NMOS).
The enable signal 165 controls the operation of the first transistor 110 and accordingly the connection of the second and the third transistors 115, 120 to the first source 160. Thus, the enable signal 165 is used to control the timing of the output clock signal from the second and third transistors 115, 120. The buffer 100 is used to minimize supply related noise and degradation from unmatched rise and fall times. That is, the buffer 100 is used to make the clock edges sharp. However, variations in the parameters of the devices within the buffer (e.g., between the second and third transistors 115, 120; between the first and second resistors 130, 135) that may be caused by process, voltage, or temperature (PVT) variations may increase duty cycle error for the clock.
One approach to correcting the duty cycle error is to utilize duty-cycle correctors at the end of each clock path. These duty cycle correctors must be made very large and consume large amounts of power for them to work well when statistical variation is applied.